1. Background of the Invention
The present invention relates to a transparent latch circuit, and more particularly, to a transparent latch circuit for which a scan test is enabled.
2. Background Art
A large and complicated semiconductor device includes a plurality of transparent latch circuits and a plurality of flip-flop circuits. A transparent latch circuit TL is shown in FIG. 7, and a flip-flop circuit FF is shown in FIG. 8. The flip-flop circuit FF is constituted by two transparent latch circuits TL.
A scan test is conducted to determine whether a fault has occurred in a logic circuit (hereinafter referred to as a logic cone). For the scan test, a plurality of flip-flop circuits in a semiconductor device are connected in series to form a shift register, and a signal (a function data signal) output by a desired logic cone is shifted sequentially by the shift register, and is output externally. Designing a semiconductor device on the assumption of this scan test is called scan design, and the state wherein the flip-flop circuits are connected in series for the scan test is called a scan path.
As scan designs, there are a GSD (a General Scan Design) prepared on the assumption a scan test will be performed using a one-phase clock signal, and an LSSD (a Level Sensitive Scan Design) prepared on the assumption of a scan test using a two-phase clock signal. The merit of the LSSD is that no timing error will occur because a scan test will be conducted by using two independent clock signals; however, once the circuit structure has been completed, the size of the circuit will be increased. On the other hand, the circuit structure of the GSD can be simplified, compared with that of the LSSD, and the size of the circuit can be reduced.
However, since according to the GSD a one-phase signal is employed, the transparent latch circuits TL, which hold signals or permit the signal to pass through, in consonance with the level (H or L) of the clock signal, can not be used as part of the scan chain, while the plurality of flip-flop circuits FF that read or output signals at the leading (or trailing) edge of the clock signal are employed as part of the scan chain.
While referring to FIG. 9, an explanation will be given for the performance of a scan test when a plurality of flip-flop circuits FF1 to FF5 in a semiconductor device are located between logic cones 500 and 501. A signal (a function data signal DI) output by the logic cone 500 is transmitted through multiplexers MP1 to MP5 to the respective flip-flop circuits FF1 to FF5. During a scan test, the flip-flop circuits FF1 to FF5 are connected in series to form a scan chain. The function data signal output by a combinational circuit 400 in the logic cone 500 is transmitted through the multiplexer MP1 to the flip-flop circuit FF1, and following this, the multiplexer MP1 selects a scan data signal SI and transmits this signal SI to the flip-flop circuit FF1. Based on a clock signal CLK, the function data signal DI is sequentially shifted from the flip-flop circuit FF1 to FF2 and then to FF3, and finally, is output by an output node 502. In this manner, when the scan chain is formed of multiple flip-flop circuits FF1 to FF5, the scan data signal DI transmitted by a desired combinational circuit 400 can be output externally.
However, when as is shown in FIG. 10 a transparent latch circuit TL is provided for the scan chain instead of the flip-flop circuit FF1, the scan chain does not function as a shift register. At the succeeding stage, the transparent latch circuit TL can not transmit, to the flip-flop circuit FF2, data received at the leading edge or the trailing edge of the clock signal CLK.
Therefore, when the transparent latch circuit TL is arranged instead of the flip-flop circuit FF1, at the scan test time, a test signal TE is externally received by the transparent latch circuit TL, so that the transparent latch circuit TL is used as a through buffer, and the flip-flop circuits FF2 to FF5 constitute the scan chain. As a result, the function data signal DI transmitted by the combinational circuit 400 can not be output externally.
When the transparent latch circuit TL is considered to be part of the logic cone 500, output data can not be uniquely defined relative to input data for the logic cone 500 that includes the transparent circuit TL. This is true because, since the transparent circuit TL permits data to pass through, a loop is generated. Therefore, the transparent latch circuit TL can not also be regarded as part of the logic cone 500.
Thus, according to the GSD, a scan test can not be performed for the wrapper or cycle stealing, of a memory circuit that employs the transparent latch circuit. And as a result, overall test coverage of the semiconductor device is reduced.
The following references are noted:                Japanese Laid-Open Patent Publication No. Hei 4-216643;        Japanese Laid-Open Patent Publication No. Hei 3-111776;        Japanese Laid-Open Patent Publication No. Sho 60-254740; and        Japanese Laid-Open Patent Publication No. Sho 57-106238.        